The present invention relates to a mask ROM (Read Only Memory) and in particular, to a NOR-type mask ROM.
One type of large-capacity mask ROM memory cell is a NOR-type of mask ROM in which a source and a drain of a memory cell are formed by an N.sup.+ diffusion layer, and a word line is arranged so as to intersect this N.sup.+ diffusion layer. A bit line is provided so as to intersect with this word line. The application of a read current to this intersecting word line and bit line enables a required memory cell to be selected. In this NOR-type mask ROM, one main bit line and one ground line are provided in parallel to select one of two adjacent columns of memory cells, and between them are provided two bit lines for selecting one of the two memory cells. When the ground line is fixedly provided, a dead path occurs in the direction of the width of the bit line of the entire memory and so there has been proposed a technique to provide this ground line as a so-called virtual ground line. More specifically, the virtual ground line is a ground line which is configured so that it is in connection with only a source side of a selected cell when that cell is selected.
FIGS. 1 and 2 show respectively, a circuit configuration of a memory cell array of a mask ROM provided with the virtual ground line having such a configuration, and a plan view of a memory cell array.
In FIG. 1, a bit line 1 which is arranged in the up and down direction is formed by an N.sup.+ diffusion layer, and a word line 2 which is arranged to the left and right of it are formed by polycide. The bit line 1 and the word line 2 are arranged so as to intersect, and a source and drain region of the MOS transistor is formed at the intersecting portion, and a flat cell 3 which forms a channel of the MOS transistor has a NOR-type configuration. The configuration is such that a means such as differences in the amounts of diffused impurities to the channel is used for the flat cell 3 to conduct or not conduct by a required gate voltage which corresponds to the information bit which the-cell is to hold. The flat cell has the N.sup.+ diffusion layer as the bit line and so in order to increase the connection capacitance and the resistance, a bank selector circuit configuration, not shown in the figure, is used so that a large reduction in the two makes use of the NOR type which is characteristic of the flat cell and enables high-speed read. Each bank is configured from an even-numbered bank selector transistor 4 and an odd-numbered bank selector transistor 5 which are each connected to each end of the bit line 1, and 16 memory cells which have the 16 word lines WL.sub.0 -WL.sub.15 as the gate electrodes, with the memory array being divided into 256 banks in the direction of the bit line 1. The bit line 1 is connected to a main bit line 6 which is formed of aluminum (hereinafter abbreviated to A1) and via the even-numbered bank selector transistor 4 and the odd-numbered bank selector transistor 5. The lower end portion of the main bit line 6 is connected to a sense amplifier 14 via a column selector transistor 13 which is controlled by a column selector line CS. A virtual ground line 7 is also formed by A1, and is connected to the source of the memory cell transistor 3 via the even-numbered bank selector transistor 4 and the odd-numbered bank selector transistor 5. The lower end portion of the virtual ground line 7 is connected via a virtual ground selector transistor 15 which is controlled by a virtual ground selector line VS and the column selector transistor 13. The main bit line 6 and the virtual ground line 7 are arranged so that they are adjacent. The memory cell relates to either the even-numbered columns 8 or the odd-numbered columns 9 and it is possible to select either the even-numbered columns 8 or the odd-numbered columns 9 by switching the even-numbered bank selector transistor 4 and the odd-numbered bank selector transistor 5 at both ends of the bit line 1.
For example, a read operation for even-numbered columns involves both an even-numbered column-bank selector line 10 and one word line such as the word line WL.sub.15, becoming the "Hi" level when they are selected, and the source and the drain of a memory cell 3a being connected to the main bit line 6 and the virtual ground line 7 of A1. At this time, an odd-numbered column bank selector line 11 becomes the "Lo" level and the odd-numbered bank selector transistor 5 turns off. A "Hi" level is also impressed to an odd-numbered column memory cell 3b by the word line WL.sub.15 but across the source and the drain of the odd-numbered column memory cell is shorted by the even-numbered bank selector transistor 4 which is in the on status, the memory cell 3b is off.
Accordingly, when the even-numbered column bank selector line 10 of bank i, and the word line WL.sub.15 are selected, the presence or absence of a current passing through the memory cell 3a reads the contents stored in the memory cell 3a to the sense amplifier 14. Read operations of the memory cells of odd-numbered columns are performed in a similar manner.
As has been described above, the main bit line 6 and the virtual ground line 7 are formed of A1 wiring and in addition to connecting the A1-N.sup.+ diffused connection 12 arranged so as to perform selection of even-numbered columns and odd-numbered columns, also performs zig-zag wiring in the direction of the columns. The A1 line pitch is twice that of the N.sup.+ diffusion bit line pitch, and the configuration is such that it is possible to greatly reduce the coupling noise and shorting between the A1 and so ensure sufficient space between the A1.
However, with such a conventional configuration, the memory cell columns formed between the main bit line and the virtual ground line are 1/2 column, 1 column and 1/2 by the two bit lines. The memory cells are one each in the direction of the word line and so the chip size increases by this portion. This influence increases for the larger the number of divisions of the memory cell array, and is a problem for large-capacity mask ROM. In addition, since the A1 main bit line and the virtual ground line are bent in a zig-zag to select the even-numbered columns and the odd-numbered columns, the wiring length becomes longer by this portion to the disadvantage of high-speed operation. The zig-zag configuration of the main bit line and the virtual ground line places restrictions on the configuration due to the principle of operation of mask ROM.